	module bcd_2(SW0,SW1,SW2,SW3,HEX0,HEX1,HEX2,HEX4,HEX5,HEX6,HEX7);
	input [3:0]SW0,SW1,SW2,SW3;
	output [0:6] HEX0,HEX1,HEX2,HEX4,HEX5,HEX6,HEX7;
	reg[3:0]m0,ST0,ST1,ST2;
	reg [4:0] SS,MM;

	bcd_22 t1(SW0,HEX4);
	bcd_22 t2(SW1,HEX5);
	bcd_22 t3(SW2,HEX6);
	bcd_22 t4(SW3,HEX7);

	always @(*) 
		begin 
			SS = SW0 + SW2;
			MM = SW1 +SW3;
			if(SS>=4'b1010)
				begin
					if(MM>=4'b1010)
						begin
							ST2=4'b0001;
							ST1=MM-4'b1001;
							ST0=SS-4'b1010;
						end
					else begin
						ST2=4'b0000;
						ST1=MM+4'b0001;
						ST0=SS-4'b1010;
						end
				end
			else if(MM>=4'b1010)
				begin
					ST2=4'b0001;
					ST1=MM-4'b1010;
					ST0=SS;
				end
			else begin
				ST2=4'b0000;
				ST1=MM;
				ST0=SS;
				end
		end

	bcd_22 u1(ST0,HEX0);
	bcd_22 u2(ST1,HEX1);
	bcd_22 u3(ST2,HEX2);
endmodule

module bcd_22(SW,HEX);
	input [3:0]SW;
	output reg[0:6] HEX;

	always @(*) begin
		case(SW)
			4'b0000: HEX=~7'b1111110;
			4'b0001: HEX=~7'b0110000;
			4'b0010: HEX=~7'b1101101;
			4'b0011: HEX=~7'b1111001;
			4'b0100: HEX=~7'b0110011;
			4'b0101: HEX=~7'b1011011;
			4'b0110: HEX=~7'b1011111;
			4'b0111: HEX=~7'b1110000;
			4'b1000: HEX=~7'b1111111;
			4'b1001: HEX=~7'b1111011;
			default: HEX=~7'b0000000;
		endcase
	end
endmodule

module bcd_21(ST,HEX);
	input [3:0]ST;
	output reg[0:6] HEX;

	always @(*) begin
		case(ST)
			4'b0000: HEX=~7'b1111110;
			4'b0001: HEX=~7'b0110000;
			4'b0010: HEX=~7'b1101101;
			4'b0011: HEX=~7'b1111001;
			4'b0100: HEX=~7'b0110011;
			4'b0101: HEX=~7'b1011011;
			4'b0110: HEX=~7'b1011111;
			4'b0111: HEX=~7'b1110000;
			4'b1000: HEX=~7'b1111111;
			4'b1001: HEX=~7'b1111011;
			default: HEX=~7'b0000000;
		endcase
	end
endmodule
